Negar Reiskarimian
Ph.D. Thesis   

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  • Highly-Linear Integrated Magnetic-Free Circulator-Receiver for Full-Duplex Wireless:
    In this work, we present a novel full-duplex receiver architecture which (i) merges a magnetic-free passive N-path-filter-based non-reciprocal circulator with a down-converting mixer and (ii) incorporates an on-chip balance network into the circulator to enhance the TX-RX isolation. These innovations lower the overall power and receiver NF while substantially enhancing the TX power-handling when compared with prior full-duplex receivers that integrate a shared-antenna interface on chip. Measurement results reveal 1.8dB TX-ANT loss at center frequency and less than 3dB loss over 0.61-0.975GHz, 40dB average TX-RX isolation over 20MHz BW, 6.3dB/8dB NF w/o and with balance network optimization, +8dBm of TX power-handling which results in RX 1dB gain compression and more than 80dB total self-interference cancellation (SIC) for TX main and IM3 tones in conjunction with digital cancellation.

  • Magnetic-free Non-Reciprocity Based on Staggered Commutation:
    Lorentz reciprocity is a fundamental characteristic of vast majority of electronic structures, which can be broken by violating one of the necessary conditions of time invariance, linearity or isotropy. In recent year, exploiting time-variance, specifically spatio-temporal permittivity modulation has been explored in literature. Circuit implementations of permittivity modulation uses varactors which have a low modulation index (ON/OFF ratio) resulting in large form factor, increased loss as well as increased nonlinearity.
    In this work we have demonstrated the world's first CMOS passive magnetic-free circulator. The circulator is based on staggered commutation (phase-shifting N-path filters), a form of spatio-temporal conductance modulation. Since conductivity in semiconductors can be modulated over a wide range (CMOS transistor ON/OFF conductance ratio can be as high as 1000 - 100000), our structure is able to break reciprocity within a compact form factor with very low loss and high linearity. The prototype is implemented in 65nm CMOS technology with approximate overall dimensions of λ/80 x λ/80 at 750MHz, with measured 1.7dB loss for both TX and RX paths and up to 50dB TX-RX isolation. Our implementation also benefits from a linearity improvement technique, which improves the transmitter side linearity performance. Measurements confirm two orders of magnitude IIP3 enhancement when comparing the cases of excitations at the TX port and ANT port (TX-ANT IIP3: +27.5dBm, ANT-RX IIP3: +8.7dBm).

  • Design of All-Passive Higher-Order CMOS N-Path Filters:
    N-path filters are a promising solution to realize highly-linear, high-Q tunable on-chip filters. However, the original topology only results in a second-order filtering profile which may not be sufficient for many applications. Recent research efforts to realize higher-order N-path filter responses have relied on the incorporation of active circuitry in the filter topology. In this work a design methodology for synthesizing all-passive higher-order N-path filters is introduced and demonstrated with a 6th-order 65nm CMOS prototype which achieves 35% tuning range from 600-850MHz and an in-band P1dB of 0dBm.

M.Sc. Thesis Project

  • Variable Bandwidth TIA/Limiter for optical Links with Maximum Sensitivity:
    Design of a variable bandwidth diversity receiver to mitigate the effects of atmospheric turbulence in Free Space Optical (FSO) links by controlling the total noise power. A comprehensive study of various loss factors in an FSO system was done as part of this project as well as a GUI design for calculating loss based on the physical parameters of an FSO system in MATLAB and finally an integrated circuit design for a chain of TIA and limiting amplifier in 0.18um technology in Cadence.